It is not enough for an artificial intelligence model to be accurate when it is part of a system that senses the physical world and makes decisions that directly affect it. According to a Cadence paper published through Semiconductor Engineering on September 30, 2026, physical AI systems must operate within strict limits that include latency, power consumption, heat, reliability, and environmental conditions, because delays or inconsistent behavior may affect equipment, processes, or human safety.
From Edge AI to a Closed-Loop Control System
The article defines physical AI as an extension of artificial intelligence to systems that sense and interpret the world and then act within it. It goes beyond the traditional concept of edge AI because inference here is part of a closed loop that combines sensing, decision-making, and execution within defined operating timeframes.
The loop begins by capturing sensor data, then processing and interpreting it and converting it into an action. For this cycle to remain predictable, memory, computing, communications, and input/output resources must be coordinated. Delays in data arrival, fluctuating memory access, poor communication efficiency, or synchronization overhead may change how the system responds, even if the AI model itself is operating as expected.
Why Is a Centralized Architecture Not Enough?
Cadence points out that many physical AI applications cannot wait for sensor data to be sent to a remote centralized architecture. The data may be large or repetitive, or the decisions may be highly sensitive to time or safety. Local processing therefore becomes a practical necessity, not merely an option for improving performance.
However, moving inference to the edge introduces additional constraints. Edge devices may operate with limited power budgets and be exposed to thermal changes, vibration, motion, shock, humidity, and other physical conditions. This means the design must ensure the required response outside the stable environment of a laboratory or data center.
What Changes in Practice at the Chip Level?
These requirements extend to hardware design decisions, including memory interfaces, interconnects, input/output systems, and connections between chips. These components do not merely transport data; they also determine how it is exchanged and synchronized within the system, and therefore affect the duration of the complete cycle between sensing and action.
Devices also generally do not operate in isolation. The architecture may span an edge device, an industrial environment, or a vehicle and cloud, adding further limits to information exchange and coordination. Thus, data-movement and synchronization problems are not confined to a single chip; they may affect system behavior across several layers.
certi.news's Perspective
The core value of this perspective is that it shifts the discussion from the size of the AI model to the ability of the entire system to operate predictably. The actual change is that memory, communications, power, heat, and environmental conditions become part of the control path, rather than secondary implementation details.
However, the article does not provide architectural specifications, performance figures, or test results for a specific application; it presents a general engineering framework based on the constraints of physical systems. Questions such as how to precisely balance accuracy, latency, and power, and how to verify reliability under different operating conditions, therefore remain open for the design of each system individually.