IBM has made significant progress on its path toward building its fault-tolerant quantum computer, known as IBM Quantum Starling, which is scheduled for release by 2029 to lead a new phase in quantum computing capable of executing 100 million operations on 200 quantum bits.
The engineering architecture of the Starling computer is based on qLDPC error correction codes and relies on a modular design that reduces resource requirements by approximately tenfold compared to previous traditional systems. During the latest update, IBM announced achievements in six parallel technical areas that support this direction.
Physical Progress and Interconnect Technologies
The company has successfully validated the c-couplers technology, which allows for dense, non-local connectivity between quantum bits across the chip. The number of interconnect layers used has been increased to three, with plans to exceed this, alongside achieving a quality factor exceeding 10 million for resonators. Furthermore, improvements to qLDPC codes and interconnect designs have resulted in reducing the number of Josephson junctions required from approximately 5,000 to 2,000, which enhances production yield and processor functionality.
Decoding and Modular Cryogenic Systems
In the field of algorithms, researchers have developed the Relay-BP decoding algorithm to meet the performance requirements of the Starling computer while reducing computational overhead. The company is also working on developing a custom chip for real-time error processing using 2nm nanosheet technology.
Regarding infrastructure, IBM has introduced a new modular cryogenic design based on rectangular-shaped refrigerators that allow for the seamless connection of processing units, in addition to using high-quality coaxial cables with magnetic shielding to connect processors via long-range l-couplers.
Why Does This Development Matter?
This progress represents a practical step toward overcoming the challenges of scaling in quantum computing by breaking down engineering complexities and distributing them across modular, miniaturized units. By integrating cryogenic control chips (ASICs) that match the performance of room-temperature electronics and reducing reliance on dense, noise-inducing wiring, IBM is moving one step closer to achieving practical, fault-tolerant quantum computing by the end of the current decade.