HBM4 represents a turning point in how high-bandwidth memory is designed, as it enables the standard base logic die to be replaced with one customized for specific workloads or processors. This gives hyperscalers, in particular, the ability to align memory with custom XPU processing units rather than settling for a standard product available to everyone.
This does not mean the emergence of a new standardized product that can be purchased in the same way as conventional HBM packages. Every custom-memory, or cHBM, implementation requires an agreement specifying who designs the base die, who manufactures and tests the wafer, who integrates the memory layers, and who performs the final test. According to the material, the answers will vary depending on the project and the customers involved.
What Changed with HBM4?
An HBM package consists of multiple layers, most of them memory dies, while a logic die at the bottom handles management, addressing, and control tasks within the package. Up to HBM3, memory companies, including Micron, Samsung, and SK hynix, designed and manufactured all the dies, including the base die.
With HBM4, however, the base die has moved to more advanced logic manufacturing processes instead of using a process close to those used for DRAM. It is likely to rely on 4-nanometer or newer nodes, while the DRAM dies themselves will not move to these processes. A logic foundry can therefore manufacture the base die, after which the memory company assembles and tests the package in the standard version.
HBM4 and later generations add the option of replacing this standard die with a customized one. The memory layers themselves do not necessarily change; rather, customization focuses on control logic, interfaces, and management features, allowing the package to be aligned with the system design.
Why Does Customization Target Hyperscalers?
Using standard HBM requires purchasing ready-made units, whereas customization turns memory procurement into a design project requiring funding, a team, tools, and time. This makes hyperscalers the clearest candidates: they have the necessary resources, and their AI workloads are more specialized than those of general web servers.
These companies may dedicate large clusters of machines to a specific type of task, making it more worthwhile to modify the processor and memory together. The pace of AI-computing development is also faster than the pace of standards development. Khurram Malik of Marvell noted that JEDEC’s slow standardization process does not keep pace with hyperscalers, so customization may give them a way to respond to new workloads without waiting for an official standard.
Enterprise companies have also begun evaluating the construction of their own custom XPU units, but this trend remains at an early stage. Marvell offers a practical example through its custom cloud-computing division, where it develops XPU units for customers and seeks to design a custom HBM version capable of meeting the requirements of several customers rather than building a completely separate solution for each one.
What Changes in Practice in Chip Design?
When the base die is customized, the memory controller moves from the host processor chip into the HBM base die. This requires agreement on how the processor will connect to the controller, whether through AXI, Arm’s Advanced eXtensible Interface, or another methodology. The communication interface between the processor and the memory package can also be optimized to suit the system.
This change frees space on the processing chip because the memory controller and its associated PHY interface no longer need to drive signals between separate chips in the traditional manner. Malik said that replacing the DRAM PHY with a die-to-die interface such as UCIe could make the communication block approximately 70% smaller than a standard PHY, potentially enabling a 25% increase in computing capabilities on the processor chip, while reducing power and improving the efficiency of the XPU as a whole.
The customized base die may also provide a larger connection area, or what is known as the chip’s “coastline,” which could allow more HBM packages to be connected and increase the memory capacity available to computing units. Customization may also include reliability, availability, and serviceability functions, as well as the collection and management of telemetry data within the system.
Who Designs and Builds the Package?
Design appears to be the most difficult stage of the project’s four stages: design, wafer manufacturing and testing, assembly, and final testing. It requires an engineering team, tools, and a clear understanding of how increasing or modifying memory will affect performance and power. Although memory companies have the expertise, their resources are occupied with meeting current demand, and they may not have dedicated teams to execute a large number of custom designs.
For this reason, the design may be handled by the memory customer itself, such as a hyperscaler, or by a fabless design company such as Marvell. Even when ready-made design blocks are reused, customer-specific tuning and optimization will still be required because the requirements of hyperscalers are not identical.
Wafer manufacturing and testing are expected to take place at a logic foundry, which may not be the foundry producing the standard base die. The project agreement will determine which party is responsible for assembly. In standard HBM4, the memory company receives the tested logic die, assembles the package, and tests the final product. In cHBM, the memory company, logic foundry, and specialized assembly facility may share these responsibilities, or the customer may retain greater ownership of integration.
TSMC recently announced a collaboration with Winbond, in which Winbond supplies the memory dies and TSMC handles package assembly. This model indicates that package integration may not remain limited to the major memory companies.
Does cHBM Ease Memory Shortage Pressure?
Synopsys does not expect more than 20 projects per year to use an alternative custom DRAM stacking approach, reflecting the limited scale of this path. cHBM also does not necessarily add to total market demand; total memory demand will include both standard and custom applications, so the impact concerns the product mix more than an increase in overall demand.
Nevertheless, obtaining memory remains difficult. Malik noted that the available capacity at memory-supplier factories has been sold out for approximately a year and a half or two years, with prices rising. Supply planning may become more complicated because forecasting the number of custom projects and their manufacturing locations is more difficult than planning for standard packages.
Why Does This Development Matter?
cHBM shows that competition in AI systems is not only about increasing memory capacity, but also about integrating memory, the processing unit, and interfaces into a single design. Custom packages may reach data centers within one or two years for projects currently underway, but their adoption will remain constrained by design costs, the availability of engineering teams, and partners’ ability to perform assembly and testing. The market’s future therefore appears likely to involve multiple models rather than a single solution suitable for all customers.