The semiconductor industry is approaching a stage in which nFET and pFET transistors are stacked on top of one another within a single structure known as CFET, rather than being placed side by side as in current nanosheet transistors. Leading companies are expected to begin introducing this structure into production around 2031, according to imec’s roadmap, with a potential increase in transistor density of approximately 40%, a 50% performance improvement, and an increase in energy efficiency of up to 70% compared with current arrangements, according to the estimates cited in the article.
However, the theoretical gains do not depend on stacking alone. Each additional transistor imposes a more complex network of vertical interconnects between the layers, from the transistors to the signal lines above them, and to the power network located on the backside of the wafer. Interconnect design, material selection, and control of manufacturing steps therefore become factors as critical as forming the channels themselves.
Different Paths to One Structure
Intel, Samsung, TSMC, and IBM are developing CFET, but each company is testing a different method for connecting the layers. Most approaches favor monolithic fabrication, in which the stacked layers are built within a single integrated manufacturing flow. IBM, however, is adopting a sequential approach in which the first transistor set is fully fabricated before the second set is added, with a slight offset between the two layers to facilitate the connection of power and signal lines.
Intel is also exploring monolithic flows, along with an approach based on a hybrid substrate that allows the best type of silicon to be used for each transistor. The company uses silicon with a (100) orientation for the nFET and crystalline silicon with a (110) orientation for the pFET, then combines the two layers using a layer-transfer technique. According to the cited results, this arrangement can achieve an effective 3X increase in carrier mobility when a (110) pFET is stacked above a (100) nFET.
IBM, which licenses its CFET designs to Rapidus, offset the upper nanosheets by 10nm and said this provided 20nm of cell-height reduction. The company demonstrated active-to-active distances of 50nm in the lower section and 30nm in the upper section, with a gate-cut thickness of 20nm, enabling a 40% reduction in cell height compared with unstacked nanosheet transistors.
Samsung uses an innovative insulating structure to separate the upper and lower gate regions. In a recent presentation, the company explained that it fabricated CFET transistors with a 42nm gate pitch and triple-stacked nanosheet channels for each transistor type, along with three epitaxial layers containing different germanium concentrations within the middle dielectric isolation region, or MDI. This helps independently control the gate dipole and work-function metal for the nFET and pFET.
TSMC, for its part, is focusing on the ability to access connection points flexibly from both sides of the wafer. Its plan includes a backside gate contact and two types of vertical contact plugs for connecting the different functional layers in SRAM cells, along with multiple techniques for controlling Multi-Vt threshold-voltage values. This technology enables a combination of low-voltage transistors for speed and high-voltage transistors to reduce power consumption.
Why Are Interconnects and Manufacturing Becoming the Bottleneck?
CFET channels consist of suspended nanosilicon sheets created on a substrate made of alternating layers of silicon and SiGe. The SiGe is selectively removed during the channel-release stage, while the sheets are surrounded by a high-k dielectric layer and a metal gate deposited using atomic layer deposition, or ALD. CFET adds an MDI region to isolate the upper gate from the lower gate, increasing the number of steps and control requirements.
Sensitivity increases with the use of backside power delivery, which appeared at the 2nm node. This approach requires advanced wafer bonding, backside thinning, and extremely precise alignment between the two sides of the wafer. Differences of no more than a few nanometers in material position or alignment can lead to significant yield losses. Warpage at the microscopic or nanoscopic level can also weaken performance and increase reliability problems.
EUV lithography likewise faces edge and line roughness, random defects associated with a low photon count, and the risk of pattern collapse when tall structures with high aspect ratios are used. Materials beneath the photoresist can improve adhesion and pattern-transfer accuracy and reduce line roughness, while ion-beam etching may help remove rough edges. Pattern transfer requires simultaneous optimization of the resist layers, the silicon hard mask, and the carbon layer.
Simulation Before Running the Wafer
Against this backdrop of complexity, multiphysics simulation and virtual manufacturing have become essential tools for exploring process paths before silicon is actually produced. Models compare placing the nFET above the pFET or vice versa, as well as direct stacking and sequential fabrication, while also measuring process windows, defect probabilities, and the effects of warpage, thickness variation, and etching.
Digital twins and factory-process simulations make it possible to reduce the number of wafers required during development stages. Expected variation at each step, such as deposition thickness or selective-etch depth, can also be entered, after which machine learning can be used to map process ranges around the nominal condition. This makes it possible to identify manufacturable options early, rather than discovering a warpage or copper-density variation problem before the tape-out stage.
What Changes in Practice?
CFET may reduce standard-cell height from approximately 5T to 4T or less, depending on the process, and may also support denser SRAM cells, such as the transition from a 6T structure to 4F2. However, reducing area will come at the cost of a greater burden in alignment, isolation, interconnection, and variation management. A comparison of the companies’ approaches suggests that leadership will not be determined by the transistor structure alone, but by each manufacturer’s ability to achieve nearly atomic-level control over materials and processes, while leveraging high-NA EUV lithography and virtual simulation to improve yield before reaching the commercial production expected around 2031.