Increasing AI capabilities in data centers is no longer tied solely to the number of processors and accelerators, but also to how these resources are distributed and connected to the rest of the system. The article presents a hybrid approach that combines keeping some resources close to the processor, expanding other resources across multiple servers, and sharing high-cost resources such as graphics processing units and NVMe storage through a shared fabric.
PCI Express, or PCIe, plays a central role in this approach because it provides a broad hardware and software ecosystem for connecting processors, graphics processing units, accelerators, SmartNIC or DPU units, and storage. However, higher transfer speeds and a growing number of connected devices create challenges that go beyond simply providing additional ports. This is where the integrated functions of PCIe switches and retimers emerge.
Three Resource-Distribution Models
The scale-up model provides the greatest proximity between the processor and accelerators, making it suitable for latency-sensitive AI workloads. However, this model encounters limits in the number of processor lanes, chassis space, power and cooling requirements, and the number of devices the server can accommodate.
Scale-out, on the other hand, distributes performance across multiple nodes using Ethernet or InfiniBand. This enables cluster growth, but adds latency and requires software capable of coordinating data and workloads between nodes.
By contrast, a disaggregated architecture separates specific resources, such as graphics processing units, storage, or SmartNIC and DPU units, from ownership by a single server, making them available through a shared fabric. This can improve resource utilization and allow computing and endpoints to scale independently, but it introduces issues involving resource contention, isolation, management, and latency.
Therefore, the article does not present any one of these models as a comprehensive substitute for the others. The practical decision is to determine which resources must remain local, which should be distributed across servers, and which justify their cost by being shared among multiple systems.
What Does PCIe 7.0 Add?
PCIe 7.0 doubles the raw transfer rate per lane compared with PCIe 6.x, reaching 128 GT/s, and provides up to 512 gigabytes per second of bidirectional bandwidth when using an x16 configuration. This increase provides more room to accommodate growing numbers of accelerators and data-transfer-intensive platforms, while maintaining backward compatibility with the broader PCIe ecosystem.
However, higher speed alone is not enough to build a scalable system. The higher signaling rate makes channel loss, reflections, crosstalk, noise, and jitter more difficult to manage. PCIe 5.0 and PCIe 6.x also remain important components in current architectures, making intergenerational compatibility a practical factor in system design.
PCIe Switches for Scaling and Traffic Management
A PCIe switch receives transactions, determines their destinations, and forwards them between upstream and downstream ports. In this way, it can increase the number of connection points, support more flexible architectures, and provide direct communication paths between connected devices.
However, the number of ports and maximum speed do not alone determine actual performance. When graphics processing units, storage, and control traffic compete for the same bandwidth, arbitration mechanisms, buffering, credit management, oversubscription policies, and head-of-line blocking avoidance become factors that affect usable performance. Each additional hop through the switch can also increase latency and create a new point of contention.
Configurability is especially important for chip design teams, as it can support different port configurations, upstream-port options, varying numbers of endpoints, and multiple traffic patterns within a single switch architecture.
Retimers for Addressing Distance and Signal Quality
When resources move farther from the processor, across longer traces on the board, connectors, cables, or expansion chassis, the electrical channel becomes more challenging. A retimer recovers the clock and data, terminates an electrical segment, and then retransmits a clean signal to the next segment.
These components give designers greater flexibility in distributing devices, but they do not make distance unlimited. Each retimed segment requires design and testing, taking into account latency, power, heat, equalization, diagnostics, and compatibility among processors, endpoints, PHY interfaces, connectors, cables, and firmware.
What Should Be Measured Before Choosing a Solution?
The article recommends beginning the evaluation with a workload and topology that represent actual use, rather than with a general specification list. Teams should identify the required bandwidth and latency, the number of incoming and outgoing connections, the level of oversubscription, the traffic mix, channel loss, power consumption, manageability, and interoperability objectives.
From this perspective, PCIe switches provide scalability and traffic routing, while retimers extend usable distance and preserve signal integrity. The article mentions Rambus solutions for PCIe switches and retimer controllers as design building blocks for ASIC and FPGA implementations, but practical value is measured less by the component's name than by how well it fits the system's workload, topology, and electrical constraints.
Editorial reading: The actual change here is not the launch of a new standard or product, but a shift in the AI infrastructure design decision from asking about maximum speed to balancing proximity, scalability, resource utilization, and signal quality. The fundamental constraints remain clear: as the number of hops and shared components increases, management complexity, contention, and latency also rise. Moreover, because the article is a sponsored blog post from Rambus, it presents the framework from a marketing perspective and does not provide independent measurement results or a comparison among vendors.