Being described as an “AI agent” does not mean that a system has the same degree of autonomy in chip design. According to the framework presented in the article, capabilities range from optimizing a specific engineering task to managing a multistage workflow, while the task scope, verification method, and human responsibility remain decisive factors in evaluating any claim of autonomy.
The article presents five levels formulated by Cadence as part of its agentic AI strategy. These levels are not presented as separate product categories, since a higher level may include the capabilities of lower levels, and a higher level does not eliminate the need for basic optimization tools, design engines, and verification engines.
The Five Levels of Autonomy
- L1 — AI for optimization: The system conducts extensive experiments to tune the parameters of a specific task and achieve a goal set by the engineer. The human remains responsible for the design intent, constraints, success criteria, and trade-offs. The article cites Cadence Cerebrus AI Studio as an example of this type in executing SoC designs.
- L2 — Natural language as an interface: The system focuses on facilitating interaction with engineering tools and knowledge bases, such as answering questions or generating and correcting code. At this level, however, it does not have independent authority over the complete engineering objective.
- L3 — Complex reasoning: The agent handles a specific engineering problem, proposes an outcome, and then tests it using tools such as simulation, formal analysis, or inspection tools before repeating the process based on feedback. The engineer remains responsible for defining the problem and reviewing impactful results.
- L4 — Agentic workflow: Multiple specialized agents coordinate the planning, execution, verification, and optimization stages across interconnected tools and domains. Cadence cites the ChipStack, ViraStack, InnoStack, and AuraStack platforms as examples of applying agentic AI to design and verification, digital implementation, analog design, circuit boards, and advanced packaging.
- L5 — Full autonomy within a defined scope: The system determines its next steps based on interim results and repeats execution until closure is reached within a controlled engineering workflow. Cadence says that the ChipStack AI Super Agent operates at this level in chip design and verification flows, while allowing engineers to inspect, direct, and collaborate with its work.
The Practical Difference Between L4 and L5
The dividing line between the two levels is not the presence of multiple agents or the use of verification tools, since both may include those elements. At L4, the path remains largely controlled by the objectives, constraints, and checkpoints defined by engineers. At L5, greater responsibility shifts to the system to determine the next action according to interim results. Therefore, a system may be highly autonomous in RTL verification or front-end design without being autonomous in every design decision or in final approval.
What Should Be Examined Before Accepting a Claim of Autonomy?
The article proposes evaluating the agent through practical questions: What problem and engineering scope does it address? What decisions can it make independently? What objectives and constraints must the engineer provide? And what tools verify its outputs? It is also necessary to know what happens when verification fails or a particular constraint cannot be achieved, when the system requests human intervention, who is responsible for the alternative path, and who retains authority for final design approval.
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The real change here is not replacing the engineer with a language model, but shifting the engineer’s role from executing tool commands step by step to defining intent, monitoring results, managing exceptions, and approving sensitive decisions. The article explains that reliable autonomy in EDA requires organized design context, dependable engineering engines, and measurable results such as error logs, verification coverage, performance, power, and area indicators, in addition to a clear mechanism for intervention and rollback.
The most important limitation is that the L1 to L5 labels do not have sufficient value outside the boundaries of the workflow to which they apply. The article is also sourced from “Sponsor Blog” and was written by Vinod Khera, a marketing communications executive at Cadence; therefore, Cadence’s examples and descriptions of its products’ levels should be treated as claims by the company, not as an independent evaluation of market performance. According to the text itself, final approval responsibility remains with the engineers.