Chips and Semiconductors

SEAL Framework Enhances Security of 3D Compute-in-Memory Against Attacks

Researchers have developed a new technical framework called SEAL to reduce error vulnerabilities in 3D Compute-in-Memory processors, enhancing security for multi-tenant networks.

2026-10-25
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certi.news Editorial Team
SEAL Framework Enhances Security of 3D Compute-in-Memory Against Attacks

A research team from Arizona State University and the University of Maryland has published a technical paper introducing an innovative framework called SEAL, designed to address security challenges in 3D Compute-in-Memory (CiM) processors. This innovation aims to reduce error vulnerabilities resulting from shared power delivery networks in multi-tenant environments.

What does the SEAL framework change?

3D Compute-in-Memory processors rely on stacking various memory layers to accelerate deep neural network inference. However, sharing power resources between different users (multitenancy) creates security vulnerabilities that can be exploited. The SEAL framework intelligently optimizes the distribution of neural network layers across the physical layers of the processor, mapping the most critical and sensitive layers of the neural network to the most resilient and error-resistant physical layers.

Performance and security results

Evaluations conducted using models such as ResNet-18 and Qwen2.5-3B showed a tangible improvement in error resistance:

  • Achieving a reduction in error vulnerability by up to 3.9 times for the ResNet-18 model.
  • Achieving a reduction in error vulnerability by up to 7.8 times for the Qwen2.5-3B model.
  • In configurations heavily reliant on ReRAM memory, SEAL succeeded in placing all high-importance layers in low-error-susceptibility layers, reducing the probability of errors to the minimum technically possible.

What does this mean for users?

This approach ensures the preservation of intelligent model accuracy; the accuracy of ResNet-18 remained within 0.06 percentage points of the error-free baseline, while the Qwen2.5-3B model maintained its perplexity level within the same range. This development represents a significant step toward securing the hardware infrastructure that runs artificial intelligence, especially in data centers that rely on advanced memory technologies, where performance is not limited to speed alone but extends to security reliability against attacks targeting system stability via power networks.

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Semiconductor Engineering
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