Researchers from the Technical University of Munich (TU Munich) have published a technical paper presenting an innovative solution to accelerate transistor simulations in electronic chip design, specifically for 3nm technology based on Nanosheet architecture. The research focuses on replacing traditional Verilog-A-based transistor models with neural network-based transistor models (NN-based transistor models).
What changes in practice?
SPICE simulation is the cornerstone of integrated circuit design, but it requires massive computational resources when dealing with advanced manufacturing technologies. The new models have proven their ability to accurately predict drain current and various transistor charges, allowing for standard cell library characterization to be performed much faster.
Experimental results showed that the neural network-based models achieved the following:
- Superior Speed: Reducing the time taken for standard cell library characterization by up to 8 times compared to the industry-standard BSIM-CMG model.
- High Accuracy: Achieving very low error rates, with less than 0.11% in delay estimation and 0.76% in total power estimation across a wide range of circuits.
- Convergence Efficiency: The models demonstrated better convergence capability in Electronic Design Automation (EDA) tools, a technical challenge often faced by AI-based models in complex design environments.
Why does this news matter?
These results are an important step toward integrating artificial intelligence into chip design flows (EDA flows). While previous models struggled with rigorous testing within professional design tools, this research proved that neural models can be a practical and reliable alternative to traditional compact transistor models. The researchers also provided guidelines on the relationship between neural network size and simulation accuracy, providing a roadmap for engineers to balance simulation speed and precision.
This development opens the door to reducing design cycles and computing costs in the development of advanced chips, which is vital as transistor sizes continue to shrink and the complexity of digital and analog circuits increases.