Axiomise

From Specification to Formal Properties: AI Speeds Up Chip Design Verification but Does Not Eliminate the Engineer

Large language models are nearing the point of converting chip design specifications into formal properties in SystemVerilog Assertions, potentially reducing the time needed to prepare verification drafts. However, incomplete specifications, the possibility of producing syntactically correct but logically weak properties, and the high review burden make human oversight essential, while the actual economic return remains uncertain.