Follow the latest coverage, related explainers and connected technology stories.
Semiconductor Engineering reviewed several major developments in the chip industry, from artificial intelligence agents for chip design and Spectre-v2 threats to the expansion of advanced packaging and photonics and the shortage of engineers. The overall picture reveals that the growth of AI infrastructure is simultaneously placing pressure on memory, energy, networking, and manufacturing capacity.
The shift of AI chips toward stacked architectures and chiplet-based designs is forcing EDA tools to analyze the entire system, from the chip to the package and board, while integrating agentic AI to accelerate exploration. However, interoperability, dynamic planning, power and thermal analysis, and maintaining result accuracy remain key challenges.
An analytical article concludes that artificial intelligence will deliver the greatest value in chip design tools when it coordinates workflows across tools and teams, rather than merely optimizing a single tool. However, reliance on it remains conditional on continuity of meaning, deterministic verification, and the ability to audit every result.
The semiconductor packaging industry is exploring negative thermal expansion materials that can reduce mismatches between the expansion of the die, substrate, and surrounding mold compound, a problem that is worsening as package and panel sizes increase. However, widespread adoption of these materials still depends on their ability to operate across a broad temperature range, mix homogeneously, and control impurities.
It is not enough for a digital twin to emulate the theoretical design of a package; it must remain synchronized with what production lines actually manufacture, while linking chip, material, supplier, and test data. The article reveals that insufficient context, overlapping physical effects, and the need for continuous calibration are the main obstacles to building a digital twin for advanced chip packages.