Google revealed that researchers, working with ETH Zurich, developed customized attack patterns that bypass enhanced Target Row Refresh (TRR) defenses in DDR5 memory. This research enabled the first privilege-escalation exploit via Rowhammer on a standard production desktop system equipped with DDR5 memory, in an experiment using a modern AMD Zen processor and SK Hynix DDR5 memory.
The findings were presented in a joint research paper titled “Phoenix: Rowhammer Attacks on DDR5 with Self-Correcting Synchronization.” Google said it is still evaluating how applicable the results are to other hardware configurations. The paper is scheduled to be presented at the IEEE Security & Privacy 2026 conference in San Francisco from May 18 to 21, 2026.
How Does Rowhammer Work?
Rowhammer exploits a weakness in DRAM memory cells, which store data as electrical charges that leak over time. The system periodically refreshes the cells to prevent data loss, but discharging a cell before the refresh cycle can alter the bit stored in it.
By repeatedly accessing a row of memory, an attacker can cause changes to bits in neighboring rows. These changes may be used to corrupt data, affect memory pages allocated to other applications or the operating system, target sensitive data for privilege escalation, or cause denial of service. Protection against this type of attack is increasingly important in multi-tenant isolation environments, such as cloud infrastructure.
Existing but Bypassable Defenses
Memory systems use mechanisms such as ECC and TRR to limit Rowhammer risks. TRR monitors accesses to a limited number of rows near a target row, then requests a refresh of the affected row when the number of accesses exceeds a certain threshold. This mechanism can be integrated into the DRAM chip or the host processor.
However, this protection is not conclusive. The TRRespass attack demonstrated the ability to bypass TRR by concurrently accessing multiple non-adjacent rows, while later attacks such as Half-Double and Blacksmith introduced more efficient access patterns. Current DDR5 systems also do not support PRAC or similarly strong protection mechanisms, and therefore rely on probabilistic methods such as ECC and enhanced TRR.
Open-Source Testing Platforms
To facilitate analysis of these defenses, Google collaborated with Antmicro to develop two specialized open-source FPGA-based platforms for testing DDR5 modules:
- DDR5 RDIMM platform: A test board meeting the requirements of registered RDIMM memory commonly used in computing servers.
- SO-DIMM platform: A version supporting the standard connector for DDR5 modules used in workstations and consumer devices.
Antmicro designed and manufactured the two platforms, after which Google worked with the company and researchers from ETH Zurich to test their ability to analyze commercially available RDIMM and SO-DIMM memory modules. Studying internal TRR mechanisms requires reverse engineering proprietary mechanisms that vary between manufacturers and models, as well as issuing precise DDR commands and analyzing responses—tasks that are difficult to perform on conventional commercial systems.
The Road Ahead
Google concludes that current protection mechanisms make attacks more difficult but do not prevent them, because an attacker needs a deep understanding of the targeted memory subsystem architecture. The company believes that ECC was not originally designed as a security mechanism, and that memory encryption without cryptographic integrity does not provide useful protection against Rowhammer.
Google supports the PRAC standard approved by JEDEC, which is scheduled to be supported in upcoming versions of DDR5 and LPDDR6. The standard precisely counts activations of a DRAM word line, then alerts the system when an excessive number of activation operations is detected. Until this protection becomes available, Google continues to evaluate other measures and collaborate with academic and industry partners to improve testing platforms and analysis techniques.