Inspection Challenges in Advanced Packaging
As the semiconductor industry continues toward increasing miniaturization and greater structural complexity, traditional failure analysis methods face significant technical hurdles. Particularly prominent is the difficulty of detecting micro-cracks in extreme low-k (ELK) dielectric layers in flip-chip devices, which are heavily used in advanced packaging engineering during back-end-of-line (BEOL) manufacturing stages.
An AI-Driven Technical Solution
A research team comprising experts from Materials Center Leoben, PVA TePla, and Advanced Semiconductor Engineering (ASE) has published a technical paper proposing a novel AI-based workflow to improve the quality of scanning acoustic microscopy (SAM) images. This innovation aims to address the problem of so-called "white bumps," which are interconnect defects that are difficult to detect using conventional means.
What Changes Practically?
The new technique relies on AI-powered image processing algorithms to enhance contrast and clarity in acoustic microscopy outputs. This improvement is not limited to mere image clarification, but also contributes to:
- Increasing detection accuracy: Enabling engineers to identify cracks and structural defects that were previously considered invisible or ambiguous in conventional images.
- Improving packaging reliability: Reducing the likelihood of defective chips leaving production lines, thereby increasing the efficiency of advanced packaging processes.
- Supporting miniaturization: Providing an inspection tool capable of keeping pace with the physical challenges imposed by nanoscale dimensions in modern chips.
This step is part of the industry's ongoing efforts to integrate machine learning tools into quality control processes, as this approach reduces reliance on human judgment in interpreting complex images, thereby lowering the margin of error in high-speed manufacturing environments.