Researchers at the University of Texas at Austin presented a new research paper outlining an advanced framework named APPlace, aimed at addressing the challenges of analog and mixed-signal circuit layout automation. The innovation relies on the co-optimization of device locations and access points concurrently with the global physical layout stages.
Traditional Challenges in Analog Circuit Design
Analog circuit layout automation remains a complex task because parasitic effects and mismatch issues arising during the layout directly and critically affect circuit performance. The component placement phase is crucial as it constrains the routing solution space and determines the level of performance achievable after manufacturing.
In current analytical methods, the layout process relies on optimizing device coordinates based on centered wirelength metrics, leaving the selection of access points to the subsequent routing stage. However, routing pins in analog circuits represent extended segments of terminal metals rather than abstract fixed points, making the selection of the optimal access point fundamentally dependent on the locations of other connected devices.
How Does the New APPlace Framework Work?
The APPlace framework introduces a radical solution by integrating access point selection and device locations together during the global placement phase, followed by a legalization adjustment phase that preserves the structural architecture established by the global placement without disrupting it.
Practical experimental results on four real-world analog circuit benchmark suites demonstrated that the APPlace system achieves remarkable superiority in overall performance compared to traditional baseline models, within a comparable layout area.
What Does This Innovation Change Practically?
Ablation and evaluation studies conducted by the researchers confirmed that omitting the co-optimization of access points leads to a significant loss of up to 13 dB in the Common-Mode Rejection Ratio (CMRR) in operational transconductance amplifier (OTA) tests, in addition to a 23% increase in comparator delay.
This innovation highlights the importance of early integration between device placement and routing paths in Electronic Design Automation (EDA) tools, opening the door to improving the efficiency of complex analog and mixed-signal circuits.