The use of agentic AI in chip design is shifting from accelerating individual tasks, such as RTL generation or debugging, to running longer flows involving multiple agents and tools. But this progress does not mean that chip design has become a fully autonomous process; before deploying agents, engineers need to build what can be described as “human scaffolding”: defining domain-specific knowledge, determining design intent, and creating an operational architecture that controls tools, memory, execution loops, and checkpoints.
This conclusion emerged from a roundtable held by Semiconductor Engineering behind closed doors during the Design Automation Conference. Participants included Matt Graham from Cadence, Harrison Balistreri from ChipAgents, Alexander Petr from Keysight EDA, Sathish Balasubramanian from Siemens EDA, and Anand Thiruvengadam from Synopsys. Liz Allan, managing editor at Semiconductor Engineering, published excerpts from the discussion on August 27, 2026.
From Task Agents to Complete Design Flows
Participants said customers have begun using agentic AI in production environments to address specific pain points, while retaining human intervention for smaller tasks. Current uses include RTL generation, verification, debugging, and coverage closure, while the broader goal is to provide a specification and ultimately obtain a design that can be converted into GDS II or a chip. However, according to the discussion, this complete scenario has not yet been achieved broadly and without human intervention.
Balasubramanian said the focus is shifting from a single agent to coordinating flows or multiple subagents. Balistreri discussed complete standalone results in specific engineering flows, such as coverage closure using multi-agent swarms, provided that the organization’s context and the details of how the customer performs the work are understood. Graham pointed to expanding use from the digital design front end to analog and mixed-signal design, digital implementation, full-chip design, circuit boards, packaging, and even multiphysics flows.
In practice, this means that the scope of automation is expanding from the chip itself to a multichip ecosystem and its associated systems. Petr said investment is moving toward multichip technologies, the AI stack, and photonics because scaling is no longer based on a single chip alone. But he also noted that agents handle domains based on software and code more easily, while areas that depend on user interfaces and the mouse remain more difficult.
Ontology and the Agent Harness Before Running the Model
According to the participants, the engineer’s primary task is not to write more scripts for agents, but to describe the domain in which they will operate. Here, an ontology is an organized representation of the concepts, relationships, and knowledge specific to the design domain. Engineers need to define criteria such as power, performance, and area; acceptable limits; and the parameters that agents can explore, while connecting these to design intent and the rest of the flow stages.
The “agent harness” is the software layer surrounding the model, including tools, memory modules, execution loops, and safeguards. The discussion emphasizes that its value does not emerge merely from connecting a general-purpose language model to a tool, but from tuning it for chip-design tasks and the organization’s context. The ontology must also extend across the entire flow, rather than being limited to a single verification process or IP team, because modifications and new data move among multiple stages and teams.
Autonomy Does Not Eliminate Human Verification
There is broad agreement that confidence in the results is the most important practical obstacle. Thiruvengadam believes humans will retain two primary roles: defining design intent and verifying that results are auditable and correct. Systems should therefore present their results in a way that engineers can quickly understand and verify, with clear stopping points and an appropriate interface; otherwise, agent output will become a new bottleneck instead of removing manual work.
Balistreri argues that relying on human review of every output limits the expected benefit of autonomy. Agent loops should therefore include gates that prevent certain categories of critical errors. He cited an example involving coverage-model exemptions, in which an agent might decide to waive coverage in a location that should not be exempted, creating a significant burden for human review. By contrast, Balasubramanian and Graham stressed that language models are nondeterministic, and that their scenario selection or suggestions cannot replace deterministic, mathematically precise signoff and verification engines.
What Is Actually Changing?
The real transformation is not replacing EDA engines, but placing AI above them and connecting them within longer execution loops that are more capable of exploring the design space. Participants said customers have begun to see a positive return on investment and tangible gains in verification, implementation, and some analog and system applications, including thermal architectures and topics related to CMT, or common-mode transition.
But these results do not prove that a “single agent” will control the entire design process. The question remains open as to whether the industry will move toward one super-agent, multiple specialized agents and frameworks, or each company choosing its own framework. Token cost has also emerged as an important planning factor for customers, according to Graham, along with the need to integrate AI with the core engines that remain essential when the cost of an error is high.
Editorial reading: The data indicates that the bottleneck is shifting from writing commands to context engineering, governance, and verification. Chip-design teams with detailed knowledge of their flows will be affected more than others, but the source provides no standardized measurements of the gains and does not specify when a fully autonomous flow will be achieved. Therefore, statements about “autonomy” and a “positive return” should be treated as results reported by participants and customers, not as a general standard established for all chip-design projects.