During FMS: the Future of Memory and Storage, held in Santa Clara from August 4 to 6, 2026, Kioxia said that AI data centers need alternatives that expand the memory and storage tier alongside DRAM and HBM. The company presented flash technologies and memory modules based on the Compute Express Link (CXL) interface to address this challenge, emphasizing that conventional flash cannot simply replace DRAM because of latency and write endurance.
Why Are AI Data Centers Looking for DRAM Alternatives?
Kioxia explained that the expansion of AI data centers is increasing demand for HBM and DRAM, while supply constraints are raising the cost of these components. Expanding data center infrastructure also adds further cost. The idea of using flash in the memory tier is based on the large capacity difference: a 32-gigabit DRAM chip corresponds to a 2-terabit flash chip, meaning approximately 64 times more capacity.
However, this difference does not eliminate the technical limitations. Flash is slower for reading and writing, and its ability to withstand write operations is limited compared with DRAM. Kioxia believes that data access patterns in AI data centers provide an opportunity to distribute roles: the company indicates that approximately 20% of data may account for 80% of access operations. The most active data can remain in DRAM, while the less frequently used portion can be moved to low-latency flash.
XL-FLASH and CXL Memory
Kioxia presented XL-FLASH as low-latency flash. The company says that its read latency is less than 5 microseconds, approximately ten times lower than conventional flash, with a design targeting between 150,000 and 250,000 rewrite operations over a five-year service life. However, using XL-FLASH alone does not achieve latency comparable to DRAM, so the company demonstrated combining it with a dedicated controller and a memory module over CXL.
According to the presentation, the read latency of a CXL module combining XL-FLASH and the dedicated controller is less than 10 microseconds. In an example of a system containing a processor, a DRAM module, a CXL module, and storage, a 225-gigabyte DRAM configuration was replaced with a combination containing 148 gigabytes of DRAM and 77 gigabytes of CXL memory, with performance declining by no more than 5%, according to Kioxia. The company also stated that the same combination could double capacity and deliver approximately 1.3 times higher performance when compared with a DRAM-only system of equivalent cost.
Energy Efficiency Remains a Critical Factor in SSDs
The problem facing AI data centers is not limited to capacity and latency; SSD operating power also affects system design. Kioxia noted the transition of SSD interfaces from PCIe 5.0 to PCIe 6.0 and then PCIe 7.0, while read and write speeds remain linked to available power limits.
The company showcased the tenth generation of BiCS FLASH TLC, which increases bit density by approximately 59% compared with the eighth generation, while reducing read power consumption by 40% and write power consumption by 30%, according to the presentation data. It also stated that a package combining flash chips with an interface chip can reach a capacity of 4 terabytes. Kioxia is also working on the third generation of XL-FLASH and the tenth generation of BiCS FLASH QLC.
What Is Changing in Practice?
The technologies presented do not indicate a complete replacement for DRAM, but rather the construction of an intermediate tier between main memory and storage, used for less active data when increasing capacity is more important than achieving the lowest possible latency. Actual results remain dependent on platform support for CXL modules, as well as the controller, software, and data access pattern. The available material also covers only the first part of the MONOist report, and therefore does not include details of the four sections that Kioxia said it devoted to SSD applications in AI data centers.