Chips and Semiconductors

3D Chips Push Chip Design Tools to Rebuild the Workflow

The shift of AI chips toward stacked architectures and chiplet-based designs is forcing EDA tools to analyze the entire system, from the chip to the package and board, while integrating agentic AI to accelerate exploration. However, interoperability, dynamic planning, power and thermal analysis, and maintaining result accuracy remain key challenges.

2026-09-24
4 min read
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certi.news Editorial Team
3D Chips Push Chip Design Tools to Rebuild the Workflow

The spread of stacked chips, chiplet-based designs, and forms of heterogeneous integration is pushing electronic design automation (EDA) tool vendors beyond the traditional model that treats the cell, block, and chip as separate boundaries. Designing AI accelerators and high-performance computing systems now requires considering computing, memory, interconnect, power, and thermal factors within a single ecosystem.

Liz Allan writes in Semiconductor Engineering that EDA tools are moving toward joint analysis across multiple domains, accelerated exploration of alternatives, and the addition of assistants based on agentic AI. Instead of running separate analyzers at later stages, vendors are attempting to make multiphysics models available within a single tool, so that the effects of design decisions become visible as the design changes, rather than after it is complete.

The Problem Has Moved to the System Boundaries

The article quoted Artour Levin, vice president of AI silicon engineering at Microsoft, as saying that the most difficult problems for AI accelerators are no longer confined within the chip, but occur at the system boundaries. A single chip is insufficient to run many AI workloads, making evaluation of the system as a whole necessary.

Hardik Kabaria, CEO and co-founder of Vinci, believes that the traditional workflow developed around clear abstraction boundaries, with physical verification deferred until the end of each domain. This model becomes less suitable when heat, stress, and electrical behavior propagate across the entire physical stack. Teams therefore need physical information while making decisions, not after the design has stopped changing.

What Is Changing in Practice?

According to the article, simply accelerating legacy tools is not enough. What is required is the continuous availability of accurate, deterministic physics across the chip, package, board, and system. Kabaria emphasizes that results must be measurable and accurate enough to support actual decisions, with the reproducibility of results between runs being as important as speed.

Spatial planning is becoming more difficult as system components differ, requiring computing, memory, and interconnect units to be distributed while accounting for their mutual effects. Challenges are also emerging related to tool compatibility between vendors, dynamic planning, IR-drop analysis, and static timing analysis (STA).

Between Evolving Existing Tools and Building New Ones

This phase raises a strategic question for the EDA industry: should mature tools that have accumulated decades of knowledge be expanded, or should new tools be built to suit the ways AI and high-performance computing designs differ from traditional monolithic chips?

Henry Sheng, executive director of research and development at Synopsys, said that much of the accumulated knowledge remains important, but some assumptions that work in isolation may not hold up when moving to multidomain analysis. The challenge lies in reorganizing tools, data, and terminology within a coherent environment, rather than reinventing everything or maintaining different representations of the same concept.

certi.news Analysis

The actual change here is not merely adding an AI feature to an EDA tool, but shifting the decision point from the chip level to the system level. Agentic AI may help automate tasks and explore more alternatives, but it does not eliminate the need for accurate, reproducible simulation. Interoperability between tools, the speed of multiphysics models, and their ability to keep pace with a changing design remain open questions that will determine how successful this transformation is.

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Semiconductor Engineering
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