The Challenge of the Gap Between Specifications and Automation
The semiconductor industry faces a fundamental challenge when attempting to integrate AI into current design flows. The core problem lies not in the ability of Large Language Models (LLMs) to write code, but in the quality of the "Specifications" upon which this code is built. While AI can generate SystemVerilog Assertions (SVA) in a matter of seconds, these results depend entirely on the accuracy of the inputs, which in the current industry are often incomplete or ambiguous.
Experts point out that the true goal of AI should not merely be generating properties from natural language specifications, but rather assisting in formulating better and more accurate technical specifications. Prose-based specifications cannot be directly handled by formal tools because they lack the mathematical precision required by these tools.
What Changes Practically in the Engineer's Role?
It is a mistake to believe that automating property generation will eliminate the need for specialized verification engineers. On the contrary, this shift raises the bar for skill requirements. Instead of spending time writing assertions manually, the engineer's role will shift to the stage of "reviewing and validating AI outputs."
- Logic Verification: The engineer must ensure that the generated assertion covers the actual requirements and is not just syntactically correct code.
- Complexity Management: As System-on-Chip (SoC) complexity increases, the ability to interpret the results of formal verification tools becomes vital.
- Addressing Ambiguity: AI may not have the ability to identify contradictions in specifications, placing the burden of detecting these gaps on the human engineer.
Technical Risks: The "Vacuous Assertions" Trap
One of the most dangerous challenges facing the use of AI in this field is what is known as "Vacuous Assertions." These are assertions that appear syntactically correct and pass verification tool tests, but in reality, they do not verify any actual behavior in the design because their conditions are always automatically satisfied regardless of the chip's performance.
This type of error can lead to false confidence in design integrity, causing exorbitant costs when defects are discovered in late stages, whether in terms of consuming verification tool time or engineer time in debugging.
Towards a More Reliable Methodology
To transition from the experimental stage to stable industrial application, experts suggest several paths:
- Using RAG Technology: Enhancing AI models with "Retrieval-Augmented Generation" (RAG) to link them to specialized knowledge bases that include design rules and proven patterns, instead of relying solely on what the model learned during training.
- Formal Specification-Based Design: Moving towards writing specifications that are "machine-readable" from the start, reducing the gap between human text and mathematical logic.
- A Gradual Approach: Starting by applying automation to small, limited, and well-understood design blocks, and comparing AI outputs with results written manually by engineers before scaling to the full design.