The leading developments in the chip industry during the week ending August 21, 2026, ranged from rising manufacturing costs for some chips and major investments in AI infrastructure to research projects targeting memory, advanced packaging, and interconnection between system components. These developments combine commercial announcements, financing deals, and research findings, reflecting the expanding scope of the technical and economic challenges facing the sector.
Prices and Capacity Under Pressure
Reuters reported that Samsung raised the prices of foundry manufacturing orders using its 4nm, 5nm, and 8nm processes by up to 15%, while its 4nm line in Pyeongtaek is reportedly operating at full capacity. SMIC also raised its prices, according to comments made during the company’s earnings call last week. Separately, Gartner expects the cost of AI inference per agent workflow to increase fivefold through 2028, as the pace of innovation outstrips the cost-decline curve.
Deals and Funding Around AI Chips
Socionext added Intel 18A-P technology to its custom-chip roadmap, beginning with a high-performance computing and data-center chiplet, marking another win for Intel Foundry’s advanced process with an external customer. Marvell will also develop custom chips for Google’s TPU ecosystem, potentially including inference accelerators, NICs, and memory-interface control units, while Google will have the option to purchase up to $12.2 billion in Marvell shares.
In infrastructure, Nvidia plans to invest $1.5 billion and provide credit support to SoftBank subsidiary SB Energy, which will build and operate an 8-gigawatt data center in Ohio using Nvidia chips, with OpenAI set to lease it. Groq raised $350 million to expand its inference cloud, while Etched secured $700 million to develop rack-scale inference systems based on jointly designed chips, packages, circuit boards, cooling units, and links. Velaura AI raised $110 million to commercialize intellectual property for low-power digital chips and a design platform for XPU modules.
Investments in Research, Packaging, and Interconnects
Micron plans to spend $10 billion over the next decade to establish a new research laboratory in Boise, Idaho, focusing on memory technologies, memory-and-computing architectures, packaging, and manufacturing. Semiconductor Research Corporation also launched an industry-directed university research program with funding exceeding $13 million.
Researchers from organizations including the University of Virginia, MIT, SK hynix, UIUC, and Yonsei published a roadmap for co-packaged optics (CPO) in high-performance computing and AI applications. At the Hot Interconnects conference, Arista demonstrated a liquid-cooled optical XPO module with a capacity of 12.8 terabits per second and 64 channels, operating at 212 gigabits per second per channel and consuming approximately 130 watts in total, with performance meeting emerging requirements for the IEEE 802.3dj and 802.3df standards.
Why Does This Week Matter?
These developments show that expanding AI capabilities depends on more than the processor alone. Prices, power, cooling, memory, packaging, and interconnects have become interconnected parts of the system-building equation. This is also evident in Waymo’s disclosure of its vehicle-computing architecture, which includes a custom ASIC manufactured using a 5nm process, and in IBM’s step toward linking two ultracold units in a single environment as a prelude to modular quantum systems capable of connecting hundreds of quantum chips.
In robotics, an Intel-commissioned study found that 60% of leaders expect to operate robot fleets within five years, compared with only 40% that currently have a formal human-robot workforce strategy. The findings indicate that skills shortages, safety concerns, and inadequate edge-AI infrastructure remain practical barriers to scaling.