Thermal management is no longer a problem addressed after the chip design is complete. As power density rises and the industry moves toward multi-die packages and advanced packaging technologies, heat has become an architectural factor that affects unit placement, interconnect paths, performance, reliability, and even data center design. This was the central conclusion of a discussion organized by Semiconductor Engineering with experts from Synopsys, Silvaco, Vinci, Keysight EDA, and Siemens EDA during the Design Automation Conference.
The article, published on September 15, 2026, by Ed Sperling, does not present a single product or test result. Instead, it portrays a problem that expands as design moves from the transistor to the die, then to the package and board, and ultimately to the system, server racks, and data center. According to the participants, solutions that focus only on the heat source inside a single die are no longer sufficient for designs containing numerous chiplets and adjacent memory and communications components.
Heat Has Become an Architectural Decision
Satish Radhakrishnan, head of the semiconductor and electronics sector at Vinci, explained that the discussion has shifted from asking how much density can be placed inside the chip to broader questions: How will the components be packaged? How will heat be removed? And how much heat can be tolerated with vertical integration? This means that the choice of architecture may determine cooling and reliability capabilities before the final verification stages begin.
This decision affects an interconnected set of constraints. Lang Lin, director of product management at Synopsys, noted that the power budget, chip layout, interconnect resources, and timing budget interact with heat, which can alter delay, power consumption, signal integrity, and deformation. Chris Mueth of Keysight EDA added that performance and mechanical and thermal characteristics alone are no longer sufficient; reliability must also be included in the trade-off, particularly in high-reliability applications.
From Die Cooling to Package Cooling
According to the discussion, the industry is moving toward improving TIM 1 and TIM 2 thermal interface materials, as well as solutions such as cold plates, immersion cooling, direct-die cooling, and two-phase cooling. However, these options do not eliminate the problem; they require precise knowledge of where heat is generated inside the package and how it moves between dies and components.
Jack Berg, vice president of business development at Silvaco, noted that insufficient thermal analysis can lead to electromigration and changes in material phases, creating reliability problems. Distributing functions across chiplets does not necessarily separate thermal risks. Higher temperatures in an ASIC may affect adjacent HBM memory, while moving functions or power between components creates a need to analyze thermal and signal interactions together. The same applies to co-packaged optics when networking functions are brought closer to processing units.
Why Traditional Models Are Not Enough
With traditional methods, it was possible to evaluate general hot spots or use high, low, and medium temperature ranges and then proceed with the design. Today, however, engineers need to identify the location of the hot spot and the temperature of a specific transistor or gate, and connect that result to layout, packaging, and cooling decisions. The participants believe that thermal simulation must approach the device level while retaining sufficient computational capacity to evaluate the package and system.
This is why reduced-order models, foundational models, and digital twins are gaining prominence. Lin suggested using a simplified model of the behavior of a block or chiplet to reduce simulation costs, followed by high-fidelity analysis of critical areas. Berg believes that the architecture needs a surrogate model or digital twin at the die, package, and system levels, enabling designers to make trade-offs before reaching a stage that may require a redesign.
What Is Changing in Practice?
The most important change is the timing and scope of the decision. Thermal simulation is no longer the responsibility of a single team at the end of the design cycle; it has become a joint process that begins with architectural planning and continues through packaging, manufacturing, and cooling. This requires compatible mechanical, thermal, and electrical solvers because the effects do not operate in isolation. Mueth distinguishes between separate solvers, solvers coupled iteratively, and directly coupled solvers. Directly coupled solutions for stress and thermal analysis are now available for some manufacturing problems, such as chiplet packages and thermocompression bonding.
The broader system scope also requires distributing levels of fidelity. An engineer developing a die needs more detail than the person responsible for the package or system. Therefore, a single model cannot be used at the same level of fidelity for every stage of the process. The article also mentions trends toward using an agentic MCP, or Model Context Protocol, approach to coordinate models and tools, but cautions that artificial intelligence can make mistakes and that tracing the reason behind the decision it produced may be difficult.
Editorial reading from certi.news: What is actually changing is not the emergence of a single cooling technology, but the transformation of heat into a constraint that participates in the selection of the architecture itself. The practical benefit lies in reducing the likelihood of discovering bottlenecks after the design is complete, but the source does not establish that digital twins or AI-based models have solved the problems of accuracy or scalability. The trade-off between modeling speed and accuracy, consistency among different physics solvers, and responsibility when an automated decision is adopted also remain open questions for design tools and engineering teams.