A technical paper published by SignatureIP states that traditional interconnect models inside systems on chip (SoCs), such as shared buses and crossbars, are approaching their practical limits as the number and diversity of compute units increase. The paper links this shift to three main pressures: heterogeneous artificial intelligence workloads, safety requirements in automotive platforms, and the transition of chip designs to chiplet architectures that require coherency to be maintained across multiple silicon dies.
From the Problem of Channel Sharing to the Problem of Scalability
Shared buses and crossbars have served the SoC sector for approximately two decades, but they become less suitable as the number of agents exchanging data and maintaining memory coherency increases. According to the paper, artificial intelligence accelerators require large numbers of heterogeneous units, while broadcast-snoop mechanisms collapse when the architecture’s ability to manage these communications is exceeded.
The problem here is not merely an increase in transfer speed. As the number of units grows, the need to manage routing, arbitration, and coherency efficiently also increases, while the centralized architecture becomes more vulnerable to bottlenecks. SignatureIP therefore presents packet-switched NoC networks as a more scalable alternative to shared channels.
Three Pressures Driving Interconnect Redesign
- Artificial intelligence: Workloads depend on specialized and diverse components, increasing the need for coherency among multiple agents rather than a simple communications model.
- Automotive: ADAS and electric-vehicle platforms require safety mechanisms compliant with ISO 26262 and ASIL-D to be integrated into the interconnect architecture itself, rather than added later as a separate solution.
- Chiplets: With reference to UCIe 2.0, the coherency problem is moving from within a single die to the boundaries between dies, requiring an interconnect capable of handling these boundaries explicitly.
The paper also states that arbitration paths in crossbar architectures face difficulty achieving timing closure at 3nm and 2nm process nodes. This means that reducing transistor size does not automatically solve the communications problem; the interconnect network itself may become a factor limiting design timing and performance.
What Do NoC Architectures and Directory-Based Coherency Offer?
SignatureIP proposes packet-switched NoC architectures with directory-based coherency to address these limitations. The basic idea, as presented in the material, is to avoid relying on broadcasting coherency requests to all units and instead use a more organized mechanism to track the parties concerned with the data. This approach aims to improve scalability as the number of agents grows and their functions diverge.
In the paper, the company presents a Compute and I/O Subsystem IP portfolio that includes C-NOC, NC-NOC, AXI2CHI, CHI2AXI, ATC, and Proxy Cache, in addition to Ethernet and Inoculator components. The material does not provide enough detail to compare the performance or power consumption of these components, or their results in actual designs; therefore, the list cannot be considered independent evidence of the superiority of any particular product.
Why Does This Matter to Chip Designers?
The actual change described by the paper is the shift of the interconnect decision from being a later detail in SoC design to an architectural element that affects scalability, safety, and timing. Teams building SoCs for artificial intelligence, automotive applications, or Chiplet-based systems are required to consider early how to manage coherency, how to move data between units or dies, and how to integrate safety functions into the communications path.
Nevertheless, the material remains a technical paper associated with the SignatureIP portfolio, not a neutral study comparing NoC with other approaches or presenting detailed measurements. Its primary value therefore lies in summarizing the forces pressuring traditional interconnect architectures and identifying a clear architectural direction, while actual adoption decisions require data on performance, power, integration, verification, and the requirements of each design.