Silvaco has unveiled details of an advanced Fab Technology Co-Optimization (FTCO) workflow designed to address the gap between ideal designs and the actual performance of Photonic Integrated Circuits (PICs). The efficiency of these circuits is often affected by realistic factors such as sidewall angles, critical dimension variations, thickness differences, and line-edge roughness—details that traditional simulations based solely on theoretical designs fail to capture accurately.
The new system combines GDS layout import, 3D process simulation, GPU-accelerated Finite-Difference Time-Domain (FDTD), Design of Experiments (DOE), alongside AI-based surrogate modeling. Technical results demonstrate that integrating actual manufacturing variables into the models enables close alignment with previously recorded experimental results.
What changes in practice?
The new workflow provides the capability to process Directional Coupler DOE tests involving 25 unique combinations of four different manufacturing variables. This model requires a massive grid size of 65 million 3D FDTD cells, yet it completes in less than 10 hours on a single workstation equipped with an NVIDIA A100 graphics card.
This integration creates a digital twin that gives engineers and non-simulation specialists an intuitive and immediate understanding of the relationship between industrial process conditions and the final performance level of the chip, which the company describes as a significant shift to facilitate the evaluation of optical designs before moving to actual production lines.
Why does this news matter?
Photonic Integrated Circuits are a fundamental pillar in the next generation of telecommunications, data centers, and high-performance computing; however, the sensitivity of light to microscopic manufacturing variations hinders their rapid commercialization. Integrating precise process simulation with GPU computational acceleration and artificial intelligence removes one of the most significant obstacles to optically predicting chip behavior, thereby shortening development cycles and reducing the high costs associated with repeated manufacturing trials.