The process of designing Systems-on-Chip (SoC) for Edge AI applications faces a growing technical challenge known as the "power wall." With the increasing need for real-time performance within strict power and thermal constraints, traditional voltage scaling is no longer sufficient. Designers are now turning toward near-threshold operation, ranging between 0.4 and 0.5 volts in advanced FinFET processes, which opens new horizons for efficiency but imposes significant design risks.
Technical Trade-offs in Low-Voltage Systems
Although reducing operating voltage directly decreases power consumption per operation, working in the near-threshold range fundamentally changes transistor behavior. The most prominent challenges include:
- Increased Delay: Delay grows non-linearly and rapidly as voltage decreases.
- Increased Variability: Circuits become more sensitive to any slight changes in voltage or ambient conditions.
- Shrinking Noise Margins: Making the design susceptible to functional errors.
- Failure of Traditional Models: Models used at nominal voltage cannot accurately predict chip behavior under these conditions.
Roles of Foundation IP
To achieve a stable and executable design, IP cannot be treated as a secondary element; it must be a central part of the design process from the beginning. Three elements play a critical role:
1. Embedded Memories: Memory is considered the largest consumer of power and area. The importance of a "dual-rail" architecture, which separates logic voltage from memory voltage, stands out, allowing for deeper voltage reduction in computing units without compromising memory stability. This technique has been proven successful in 3nm FinFET processes.
2. Logic Libraries: These libraries must be specifically designed to operate at low voltage, providing highly accurate models (such as LVF models for timing) capable of simulating non-linear voltage sensitivity.
3. I/O Units: If I/O units are not capable of operating reliably at low voltage levels, they will act as a bottleneck, preventing the utilization of core improvements and setting the minimum operating voltage for the entire system.
What Changes Practically for Designers?
Transitioning to near-threshold designs means abandoning the "design then optimize" methodology. Instead, it requires a "closed-loop methodology" that links IP, Electronic Design Automation (EDA) tools, and silicon verification. This means it is necessary to conduct early exploration of Power, Performance, and Area (PPA) trade-offs and select IP architectures that align with target voltage goals before beginning final design stages.
Tangible Results in the Industry
Practical experiments show that relying on specialized, low-voltage-optimized IP solutions can achieve remarkable results; one use case in AI neural network chips recorded a power consumption reduction of approximately 20%, while achieving all performance and area goals without any impact on the development schedule or the need for chip re-spins.