AI pressures do not lie solely in processors and HBM memory; every training or inference operation produces data that must be stored, transferred, and accessed quickly. An analysis published by Semiconductor Engineering argues that the next bottleneck in AI infrastructure may be related to how high-density NAND memory is packaged, rather than merely increasing the number of cells inside the chip.
This is an analytical reading published in a sponsored feature for Amkor, and some of the forecasts it contains should therefore be treated as industry estimates or the perspective of a player in the packaging sector, not as an announcement of a specific product. Nevertheless, the piece offers a useful picture of the engineering problems that accompany increasing storage capacity in data centers, devices, and automobiles.
Demand for NAND Is Expanding Beyond the Consumer Market
According to Yole Group data for 2024, the value of the independent memory market reached $170 billion, following an annual recovery of 78% after two years of decline. DRAM, including HBM, accounted for approximately 57% of revenue, compared with 40% for NAND. As 2026 begins, manufacturers are directing more production capacity toward HBM and advanced DRAM nodes, while HBM has exceeded 10% of the total memory market, according to the article.
This focus may limit the investment available for expanding conventional DRAM and NAND capacity at a time when demand for NAND is not declining. Data centers need SSDs for AI servers, the share of laptops supplied with SSDs is rising, and flagship phones are moving toward larger capacities. Automotive systems, particularly in electric and connected vehicles, require reliable solid-state storage to run their functions and process their data.
The article uses examples of data growth to illustrate the accumulating pressure: transferring a two-hour film from 1080p to 4K increases the data volume by approximately 4.7 times, while image sizes have grown nearly threefold with the transition from 12-megapixel to 48-megapixel phone cameras. The size of a three-minute audio clip may also increase by up to six times when moving from compressed MP3 to immersive formats such as Dolby Atmos. Encoding technologies help, but they do not eliminate the need to expand memory density.
From Dozens of Packages to a Single Package
The article presents the evolution from the perspective of the space required. In 2010, storing 2 terabytes, when planar two-dimensional NAND was dominant, required more than 50 eMMC chips, with a package size of approximately 17×22 millimeters per chip. 3D NAND then changed the trajectory beginning in 2013 by stacking cells vertically, and by 2020, architectures exceeding 100 layers had reduced the number of packages needed for the same capacity.
The next step is wafer-to-wafer hybrid bonding, which increases interconnect density and improves electrical performance at the wafer level. The article expects this approach, together with multi-die stacking, to enable architectures that could far exceed current levels and eventually reach 800 or 1,000 layers. The spread of QLC also supports increasing the capacity inside a single eMMC package to 2 terabytes, according to the trend reviewed by the source.
What Changes in Packaging in Practice?
It is not enough to make dies smaller in order to stack more of them; yield and reliability must also be maintained at the same time. The article notes that manufacturing flows designed for memory exceeding 300 layers require control of wafer stress and warpage. The tools mentioned include laser grooving, ultra-fine grinding, blade or stealth dicing, and automated optical inspection to detect cracks.
Wafer thickness may fall from approximately 700–800 micrometers to just 25–50 micrometers. At that point, post-surface processing and the removal of microscopic cracks become important for reducing stress concentration. Methods such as dice-before-grind and stealth dice-before-grind are also used to limit edge damage, while thin dies require specialized pickup tools, including needleless pickup with precisely controlled vacuum force.
In structures containing 32 dies or more, the issue becomes one of managing the entire system. Ultra-low, ultra-long wire loops maintain clearance distances, while staircase or staggered arrangements help provide space for the wires and distribute stress. Materials such as film-on-die, film-on-wire, and spacers are used to prevent die sagging and preserve connection integrity without increasing the overall height, an important constraint in phones and devices with limited space.
Why Does This Matter for Data Centers and Supply Chains?
High stacking also requires advanced compression molding to limit wire sweep, along with control of cap thickness, material balance, and the coefficient of thermal expansion. Maintaining yield depends on inspection during manufacturing stages and linking every unit to traceability data that makes it possible to detect defects early and associate them with materials, tools, or process conditions.
This is where OSAT companies—outsourced semiconductor assembly and test providers—come into focus. Not all NAND companies are integrated companies that own the entire value chain, from intellectual property and wafer fabrication through assembly and testing. The source notes that leading OSAT companies provide memory stacking, unit-level traceability, wafer-level fan-out technologies, and integrated testing. Multi-region networks have also become strategically important as companies seek more diversified and geographically balanced supply chains, although the article does not establish a timeline or a specific product for these capabilities.
The editorial conclusion is that increasing NAND capacity in the AI era does not depend on the cell path alone. Every leap in layer count or storage density raises parallel questions about thickness, thermal and stress management, connection integrity, yield, and packaging partners’ ability to manufacture at scale. What remains open is how quickly technologies such as hybrid bonding will move from forecasts and advanced engineering into stable commercial products at an appropriate cost.