Research findings from the National University of Singapore, Kyoto University, KAIST, and UNIST have revealed three approaches to addressing different challenges in chip design: scaling down copper-interconnect insulators, operating silicon carbide transistors at extremely high temperatures, and improving the stability of oxide-based vertical-channel transistors.
Carbon Insulator Combines Two Functions
Researchers from the National University of Singapore developed an atomically thin amorphous carbon film to insulate copper wires whose dimensions continue to shrink. The film maintained a dielectric constant of 1.35 at thicknesses ranging from 0.8 to 2.7 nanometers, while also preventing copper ions from passing through it and withstanding strong electric fields.
The film was fabricated using chemical vapor deposition at temperatures below 300 degrees Celsius and grown directly on silicon dioxide, copper, and cobalt. Growth extended uniformly across a four-inch wafer, including the sides and corners of patterned structures.
At a thickness of 0.8 nanometers, the film withstood an electric field of between 28 and 31 megavolts per centimeter before losing its insulating capability. The significance of the result lies in combining low-k insulation with a barrier that prevents copper migration within a single layer, which could leave more space for the copper line itself. However, the team plans to work with TSMC to test long-term reliability, scalability, and compatibility with existing manufacturing processes—areas that have not yet been resolved.
SiC Transistors for Environments Reaching 600 Degrees Celsius
Researchers from Kyoto University developed complementary junction field-effect transistors made of silicon carbide (SiC JFETs) and demonstrated their operation at a temperature of 600 degrees Celsius.
The design used a bottom gate to improve threshold-voltage control, along with well-based isolation instead of a semi-insulating substrate, with the aim of limiting leakage current at high temperatures. This structure reduced leakage to a level close to the theoretical limit expected for SiC.
The result remains at the research stage, as the team intends to develop more complex circuits, move to wafer-level production, and verify that the complete package can withstand harsh environments.
Multilayer Insulator for In-Memory Computing Circuits
Researchers from KAIST and UNIST developed a multilayer silicon nitride/silicon dioxide/silicon nitride (SiN/SiO₂/SiN) insulating structure to improve the performance of oxide-based vertical-channel transistors, a structure with potential applications in in-memory computing devices.
The structure acts as a channel for oxygen transport, helping to stably compensate for oxygen vacancies in the oxide semiconductor while simultaneously limiting undesired oxidation at the electrode. After more than ten million cycles of electrical-stress testing, the threshold-voltage shift remained below 50 millivolts. The researchers also succeeded in integrating the oxide semiconductor with conventional silicon CMOS technology.
Why Does This News Matter?
The three results address different material and engineering constraints: the density of copper interconnects, leakage at high temperatures, and instability in vertical devices. However, they do not represent ready-to-use products or commercially proven production processes; each project requires additional testing for scalability, reliability, and integration with manufacturing lines. Their current value therefore lies in offering research paths that can be evaluated, not in announcing an immediate transformation of the chip industry.