Chip testing, measurement, inspection, and manufacturing are no longer clearly separate processes as the industry moves to sub-2-nanometer nodes. As dimensions approach the angstrom range, the margin for error narrows, and very small variations, potentially as small as a single atom, can affect a chip’s behavior or reliability. An analysis published by Semiconductor Engineering on September 10, 2026, describes how these conditions are driving fabs and system designers to reorganize data and testing flows across the entire product life cycle.
In older nodes, substrate thickness and structural stability provided enough margin to isolate or address some manufacturing problems later. In advanced nodes, however, dies have become thinner, while the use of chiplets, 3D packaging, and hybrid bonding is increasing. An ordinary wafer probe could damage an oxide layer or via, while a residual nanoparticle left after removing a temporary material could turn a costly multi-die package into a defective product.
Testing Is No Longer a Single Step
According to Lee Harrison, director of automotive integrated-circuit solutions at Siemens EDA, some customers avoid inspecting bonding points that will actually be used in bonding and instead use sacrificial points to protect the final structures. As the use of hybrid bonding and ultrathin chips increases, inspection before or after bonding may become more suitable than attempting to test the hybrid connection itself, which could be damaged during measurement.
This also affects system design. Rob Kruger, director of product management for multi-die and 3D IP strategy at Synopsys, said that artificial-intelligence data centers are moving toward redundant server clusters in anticipation of manufacturing problems. A defect in a 3D interconnect or multi-die package could affect a large group of functions, not just a single path. Dies are therefore tested before and after packaging, while repair or rerouting mechanisms are used, with these approaches also being applied to UCIe and 3D communications.
In practice, this approach shifts part of the reliability margin from the individual die to the package and system levels. It also enables the use of hierarchical tests, built-in self-tests, and periodic tests during operation to detect the need for maintenance before a widespread failure occurs.
The Problem Is Not Just the Number of Defects
Inspection tools become more sensitive as structures shrink, but greater sensitivity does not necessarily mean better decisions. Prasad Bachiraju, senior director of business development at Onto Innovation, said that inspection tools may detect millions of indicators on a wafer, including normal local variations that appear to be defects. Noam Brousard, vice president of solutions engineering at proteanTecs, explained that inspection signals alone are no longer sufficient to determine whether an indicator will actually lead to a functional or reliability problem.
For this reason, fabs need to collect multiple indicators, such as process variation, temperature, and voltage, and then analyze their relationship and their actual effect on logic. Higher temperature may be normal in one case, but in a stacked structure it could reduce the timing margin in an adjacent layer because of thermal coupling or self-heating. This illustrates the difference between measuring temperature alone and determining whether the temperature has created an actual timing risk.
Measurement Accuracy Extends Inside the Package
Monitoring the wafer surface is not enough when layers become thinner and packaging density increases. Juliette Vandermeer, director of product marketing at Bruker Semiconductor, noted that the bowing known in wafers may be associated with microscopic cracking, requiring a deeper view inside the metal layers. Live X-ray diffraction imaging, also known as X-ray computed tomography, can be used to detect these problems before they lead to structural collapse.
At this stage, process specifications need to be controlled within the angstrom range, while measurement specifications must reach the sub-angstrom level, according to the analysis. An error at an early stage of layer growth, thermal control, or interface roughness can also carry its effects into the final stages, making it less realistic to isolate each step from the others.
certi.news Reading: Data Becomes a Manufacturing Layer
The most important change is not merely the addition of new measurement tools, but the transformation of data itself into a coordination layer linking design, manufacturing, packaging, testing, and operation. David Fried, chief AI officer and executive vice president at Lam Research’s Semiverse Solutions, said that simulation, modeling, and virtual optimization help reduce reliance on trying an enormous number of physical pieces to map the limits of every possible variation. However, the source does not offer a solution that eliminates complexity; hundreds of processes still have to work together, and their full variation space cannot be explored using hardware alone.
This is connected to what John Kibarian, chief executive officer at PDF Solutions, described as an orchestration layer linking product engineering data and PLM, ERP, and MES systems with manufacturing-yield data and design automation. The goal is for the chip or die to know its most suitable path before packaging and for AI systems to make decisions based on the complete picture rather than isolated data.
For chipmakers and suppliers of EDA, testing, and measurement tools, this means that competition will not be limited to the accuracy of a single tool. Companies designing 3D packages, multi-die systems, and large data centers are directly affected by their ability to detect failures, distinguish them from normal variations, and manage reliability after deployment. Open questions remain about the cost of the infrastructure needed to process this volume of data, how to standardize it among suppliers, and when automated systems can make a repair or rerouting decision without human intervention.