Synopsys, in material published in the form of a sponsored blog post, announced that it has developed what it describes as the first 112-gigabit PHY fully compatible with the OIF-CEI-112G-LINEAR-PAM4 specification, in a move aimed at reducing the power, latency, and heat costs of links in AI systems and hyperscale data centers.
This move comes as AI clusters expand and rely on thousands of accelerators operating in parallel. In these environments, links between system components become a factor affecting performance and power consumption, particularly as applications move to 800-gigabit and 1.6-terabit speeds. The material indicates that interconnects consume approximately 27% of total data center power, and that this figure has grown 46-fold since 2010.
Moving Signal Processing to the Host SerDes
Traditional optical modules typically rely on retimers and digital signal processors, or DSPs, inside the module to process the signal. These components add power consumption, latency, heat, and cost to each link. The linear optics approach instead moves signal processing to the host SerDes, while retaining essential components inside the optical module, such as linear drivers, modulators, photodiodes, and transimpedance amplifiers, or TIAs.
According to the material, this design can achieve up to a 50% reduction in power compared with traditional retimed optical modules. It may also reduce latency by cutting the number of processing stages and limit heat in dense racks of AI accelerators, in addition to simplifying the system by reducing the number of components and potential failure points.
However, removing the DSP from the module does not eliminate the processing burden; part of it is transferred to the host PHY. Therefore, this component must provide strong signal integrity, effective equalization, and reliable data recovery under real-world channel conditions, while complying with the standards needed for interoperability between products from different vendors.
112-Gigabit Compliance Testing
The OIF-CEI-112G-LINEAR-PAM4 specification defines electrical limits, test points, and compliance methods for 112-gigabit-per-lane linear links at 53 gigabaud using PAM4. The material says that standardizing these requirements reduces the need for custom tuning and separate validation for each host-to-module combination, something that is difficult to implement at scale.
On the transmit side, the characterization results presented by Synopsys showed strong signal integrity under standardized test conditions. The company said that voltage modulation amplitude, jitter, and eye-closure metrics met the limits specified in the CEI specification and exceeded them in some cases across multiple temperatures.
On the receive side, jitter tolerance tests confirmed the receiver's ability to recover data in the presence of injected sinusoidal jitter and realistic channel impairments. Synopsys links these results to the potential reduction of bit errors and retransmissions and to maintaining link stability under load, factors that are important for AI and machine learning networks.
Extending Toward Higher Speeds and Co-Packaged Optics
Synopsys says the test results confirm the 112-gigabit PHY's compliance with the specification and demonstrate the feasibility of communication between the host and the module without a DSP while maintaining signal integrity across the link. This PHY is part of a broader ecosystem that includes MAC and PCS controllers, MACsec security technology, and verification IP blocks, along with an HPC IP portfolio covering PCIe 6.x and 7.0, CXL, UALink, die-to-die links, memory interfaces, and foundational IP.
The material indicates that the Optical Internetworking Forum, OIF, has begun work on CEI-224G-Linear at 224 gigabits per lane, while the CEI-224G-LR/MR drafts are under member review. The scope of two projects for a CEI-448G framework is also being defined, with the goal of creating electrical interfaces for 3.2-terabit and 6.4-terabit links.
The source connects this trajectory with the emergence of co-packaged optics, or CPO, in which optical engines are integrated next to switching chips to eliminate the copper path. The material does not mention details about the new PHY's commercial availability or its licensing terms; therefore, the available information is limited to the product's compliance, characterization results, and technical roadmap.