Intel Foundry is expanding the scale of artificial intelligence semiconductors through advanced packaging technologies, rather than relying on a single massive chip. These technologies include Foveros for stacking chips, EMIB for connecting them with embedded silicon bridges, and EMIB-T for adding channels that deliver power directly to the chips.
These approaches make it possible to combine small, specialized chips, known as chiplets, within a single package that functions as a high-performance unit. This approach is becoming increasingly important as the size of artificial intelligence workloads grows, requiring multiple components to be connected and large amounts of data to be transferred efficiently.
New Mexico Facilities Surpass Traditional Package Limits
At Intel’s facilities in Rio Rancho, New Mexico, advanced packaging technologies are being expanded at the Fab 9 facility. The company says these operations currently allow packages to be expanded to eight times what it describes as the current industry standard, with a target of exceeding 12 times that standard by 2028.
Intel describes this trend as a transition from the era of a single large chip to a system made up of multiple chips, resembling a mosaic of silicon. According to Katie Protti, director of the Fab 9 advanced packaging facility in New Mexico, the site began in 1980 with 25 employees, while today it has 2,700 employees and 500 suppliers contributing to the rollout of advanced packaging technologies in the United States.
How Does Foveros Work?
Foveros relies on connecting specialized chiplet units to a silicon interposer before assembling them into a single system. Intel explains that the process begins with a chip-placement tool, which places the chiplet units on the silicon wafer. The wafer then moves to other equipment to integrate the system, after which the spaces beneath and around the chips are filled with an epoxy material to secure them.
In the final stage, the wafers are cut into individual packages using water-cooled blades. This approach makes it possible to combine chips with different designs or manufactured using different process nodes within a single package.
According to Intel, Foveros can help extend laptop battery life by placing circuits that consume large amounts of power on more efficient manufacturing nodes. It also enables the design of thinner devices and the placement of greater capabilities in a smaller area, including edge-computing devices.
EMIB Bridges and the Evolution of EMIB-T
EMIB uses small, high-speed silicon bridges embedded in the substrate only at the locations where the chips need them. Instead of using a large silicon interposer that connects the entire package, the technology creates direct communication paths between adjacent chips, which Intel says helps reduce cost and improve efficiency.
EMIB-T, which Intel presents as the latest development in 2026, adds channels through the bridge to deliver power directly to the chips instead of routing it around them. The aim is to improve power efficiency and route the signals required for high-bandwidth memory, or HBM, technologies.
Intel Foundry says the ability to combine chiplets from different sources and place them on the largest industrial substrates provides flexibility to support the next generation of artificial intelligence engines used in data centers.