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Researchers from Georgia Institute of Technology and Synopsys propose a six-transistor SRAM cell with a monolithic three-dimensional design at the 2nm node, using indium gallium oxide pass-gates in back-end-of-line layers. The research reports a 25% area reduction and a 42.2% reduction in write latency at the subarray level compared with a high-performance silicon baseline.
A research paper from the Georgia Institute of Technology analyzes the impact of repeated thermal-tuning operations in wafer-scale optical interconnects used to train language models based on the Mixture of Experts architecture. According to the published abstract, eliminating stalls accelerated training of Mixtral 8x7B by 2.7 times in the scenario studied.