Researchers from Georgia Institute of Technology and Synopsys have published a technical paper proposing a six-transistor (6T) SRAM cell with a monolithic three-dimensional design (Monolithic 3D or M3D) intended for the 2nm node. The design combines pass-gates made of indium gallium oxide (IGO) within back-end-of-line layers, a latch circuit built entirely from silicon nanosheets, buried power rails, and ruthenium (Ru) interconnects.
According to the paper’s published abstract, the proposed cell achieved a 25% reduction in area footprint compared with a high-performance silicon baseline. The researchers also reported a 42.2% reduction in write latency when evaluating the design at the subarray level, rather than only at the level of an individual cell.
How Was the Proposal Built?
The M3D concept relies on distributing circuit elements across vertically stacked levels instead of placing them all on the same plane. In this work, pass-gates made of IGO are used in the back-end-of-line layers, while the silicon-nanosheet-based latch circuit remains in a different structure within the cell. The paper’s title indicates that the design takes manufacturing process characteristics into account, an important consideration when evaluating circuits at advanced nodes such as 2nm.
The proposal also includes buried power rails and ruthenium interconnects. These elements appear in the material as parts of the proposed structure alongside the cell-performance analysis, but the available text does not establish that a test chip was fabricated or that the design was commercially produced.
Why Does This Matter?
SRAM is an essential component of many processors, so reducing cell area can increase the density of embedded memory within a chip. The reported reduction in write latency points to a potential benefit for storage-operation performance, particularly at the subarray level, where multiple cells are included and interconnect and control challenges differ from those of an individual cell.
The editorial reading from certi.news is that the work’s significance does not lie in launching a product, but in testing a design path that combines three-dimensional stacking with oxide materials in back-end-of-line layers within a 2nm target. Nevertheless, the reported figures remain research results associated with the design and evaluation presented in the paper. The available material does not provide sufficient details about the complete measurement methodology, manufacturing yield, cell reliability, or compatibility with actual production lines; therefore, it cannot be considered evidence of commercial readiness.
The Paper and Its Authors
The paper is titled A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node and was published on arXiv in August 2026. Its authors are Po-Chuan Wang, Dongwon Jang, Eknath Sarkar, Alexei Svizhenko, Md. Nahid Haque Shazon, Piyush Kumar, Suman Datta, and Azad Naeemi.