Researchers from University of Alberta presented a paper titled PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization, proposing a method for optimizing the locations of large blocks and standard cells in chip design by predicting final post-routing performance metrics, rather than relying on early metrics that do not accurately reflect the actual outcome.
The problem is that the placement stage directly affects performance, power, and area, collectively known as PPA. Most placement methods use half-perimeter wirelength, or HPWL, as a primary optimization objective. However, the paper notes that recent comparisons have shown an almost nonexistent correlation between HPWL and final timing metrics, including worst negative slack (WNS) and total negative slack (TNS).
From Early Metrics to Post-Routing Results
According to the abstract, this disconnect between the optimization objective and the final outcome has led to weaker PPA metrics for AI-based placement tools compared with a hierarchical baseline. The researchers also examined label accuracy across ten circuits and four stages of the design flow, concluding that HPWL and pre-routing timing metrics do not represent post-routing timing order well.
The study found that the post-global-routing stage provides a better balance between the accuracy of final-timing prediction and the cost of generating training data. Therefore, PPAPlace trains its model on labels extracted from this stage instead of using earlier metrics that are farther removed from the final outcome.
How Does PPAPlace Work?
The model relies on two complementary branches: a graph attention network that analyzes the design netlist, and a spatial convolution that processes the grid of element locations at the placement-grid level. The model predicts WNS and TNS values, then propagates the gradients of these predictions to the cell coordinates through an end-to-end differentiable process.
The researchers used these gradients in two ways. The first is PPAPlace-CoOpt, in which the prediction is added as a joint objective within the optimization loop of an analytical placement tool. The second is PPAPlace-Refine, which applies a post-placement optimization to adjust the locations of large blocks through projected gradient descent.
What Changed in Practice?
On five test circuits from the ChiPBench suite that were not included in training, PPAPlace achieved average improvements of 22% in WNS and 51% in TNS compared with the hierarchical baseline, while preserving power and routability metrics. More importantly, the researchers used the same model without retraining it for each test circuit, supporting the approach’s transferability across different designs within the scope of the experiment.
The results remain tied to the five circuits used in the evaluation and to the post-global-routing stage selected by the researchers to generate the labels. Therefore, the abstract alone does not establish that the improvements will be replicated across all EDA flows or process nodes. Details regarding computational cost, model size, and the practical availability of the code also require review of the original paper. The paper was authored by Chen, Ruogu and Jie Han, and published as an arXiv preprint under arXiv:2608.13790, with code made available according to the abstract.