Photonics in chiplet systems is no longer merely a way to replace copper links and increase bandwidth. The closer the photonic die is to the processor, the better the signal distance and energy consumption, but the system becomes correspondingly more sensitive to heat, mechanical stress, electromagnetic interference, and verification issues. As a result, integrating light within the package has become a co-design problem involving the die, package, links, and the communication network within the system.
Semiconductor companies are currently moving toward placing integrated photonic circuits (PICs) in the same package as high-performance processors, network switches, and memory dies, as part of co-packaged optics (CPO) trends. Photonic chiplet architectures have also begun appearing in early designs for artificial intelligence data centers. The source indicates that the presence of prototypes, specialized patents, and early commercial designs reflects the technology’s transition from research into a stage closer to practical readiness.
From Removable Links to Integration Within the Package
TSMC introduced the Compact Universal Photonic Engine architecture, known as COUPE, as an open framework for producing photonic chips at scale. Instead of placing the electronic control die (EIC) and photonic die (PIC) side by side on a substrate, the architecture uses vertical stacking, with the control die above the photonic die, and employs copper-to-copper hybrid bonding instead of conventional solder balls.
According to TSMC, this arrangement reduces the signal transmission distance, lowers parasitic electrical resistance to a level approaching zero, and can reduce data-transfer power consumption by up to 85%, in addition to improving space utilization in high-density artificial intelligence cluster servers. However, these electrical gains place hot control circuits very close to heat-sensitive optical components, turning the proximity advantage into a new source of complexity.
In 2.5D designs, processing, memory, electronic-interface, and photonic dies are placed side by side on a silicon interposer, organic substrate, or advanced redistribution layer. This approach is more mature and lower risk, and it allows the photonic die to be reused with different processing dies. However, the length of the link between the EIC and PIC adds parasitic capacitance and inductance that limit modulator operating speed.
Three-dimensional stacking, using hybrid bonding or microbumps, shortens the electrical connection between driver circuits, modulators, and photodetectors from millimeters to microns. This enables higher baud rates, lower drive voltage, and lower energy per bit, but makes thermal and mechanical design more difficult. The co-packaged-optics road maps of organizations such as Intel, TSMC, Ayar Labs, and Broadcom are moving in this direction.
Heat Is Not Only a Performance Problem
The refractive index of silicon changes with temperature, which can alter the optical phase and central wavelength of resonant devices. Depending on the material, small silicon rings may shift by approximately 70 to 80 picometers per degree Celsius. Therefore, a photonic circuit can remain electrically connected and operate logically while losing optical performance because the resonance is no longer aligned with the laser wavelengths.
The problem increases in vertical stacking, where SerDes and driver circuits may dissipate several watts just microns away from resonators that must remain within a narrow thermal range. Laser efficiency, power, wavelength, and lifetime also depend on temperature. Differences in thermal expansion among silicon, organic substrates, glass, copper, adhesives, III–V semiconductors, and communication fibers add stresses that may affect the die or alignment.
For this reason, cooling the processor alone is not sufficient. Thermal design must include the die stack, interposer, substrate, lid, thermal-interface materials, cold plate, optical connectors, fiber routing, and the air-flow or liquid-cooling environment. Photonic dies may use heaters, sensors, and active tuning mechanisms to compensate for drift, but these mechanisms add control circuits and operating states that must be verified.
The Verification Gap at the Optical Boundary
Electrical interfaces such as UCIe have contracts and protocols that can be analyzed using formal-verification methods, including proving the absence of deadlock states and protocol violations. However, the optical system behind this interface does not have the same level of specification and discipline, according to Ashish Darbari, CEO of Axiomise. This exposes an important gap: the electrical interface may be formally verified, while the behavior of the photonic section, thermal limits, tuning mechanism, and error probabilities remain less defined.
This becomes more sensitive because an error in a thermal-tuning algorithm may appear in the field as a physical component failure. Therefore, the source proposes treating the system as an “assume-guarantee” contract: the package guarantees a specified thermal range, and the tuning loop guarantees reaching a stable state within that range. Digital control logic, UCIe interfaces, and state machines can meanwhile be subjected to the formal-verification tools currently available.
What Changes in Practice for System Designers?
The most important lesson is that the location of the photonics should not be determined after the component has been selected. Darbari proposes starting with the data-traffic pattern, then determining whether the bottleneck is at package boundaries, at the rack level, or between racks. Guillaume Boillet of Arteris believes that the photonic die can appear to the internal network as a high-bandwidth endpoint, but the network must be capable of feeding it at the required rate.
The proposed analysis recommends defining bandwidth, latency, and power budgets first; classifying data traffic into order- and coherence-sensitive flows and other large streaming flows; and then determining which links actually need to leave the package. Only after that does selecting CPO, NPO, or the type of photonic die become a logical decision. Thermal verification and electrical-optical interfaces should also be included in architectural work, rather than postponed until the final qualification stage.
This picture does not mean that photonics will replace copper everywhere. The position attributed to Jensen Huang summarizes the direction in the phrase: use optics where necessary, and copper wherever possible. According to the article, copper remains suitable for short distances within the rack or package, while optics offers advantages in links between packages and racks and over distances where electrical links become costly in terms of energy and bandwidth. The real change is that this decision is no longer a networking decision made after silicon design; it has become an architectural constraint in which processing, packaging, and interconnect must participate from the outset.