imec presented new research results addressing two fundamental obstacles facing CFET transistors, a structure that vertically stacks nMOS and pMOS transistors to reduce the height of standard logic cells. The results include a backside-contact module that improved the performance of bottom pFETs, and a new gate-stack integration that enables multiple threshold-voltage settings without consuming a large amount of additional area.
The presentation appeared in the first part of a two-part article published by Semiconductor Engineering on September 1, 2026, prepared by Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi. The first part focuses on CFET integration modules, while the second addresses design-technology co-optimization (DTCO) studies and standard-cell configurations.
Why Is the Industry Moving Toward CFET?
Advanced logic nodes currently use gate-all-around (GAA) transistors built on nanosheets, which have gradually replaced FinFETs at 3-nanometer nodes and beyond. According to the roadmap on which imec is basing its work, nanosheet GAA can continue scaling through the A10 generation, with standard cells at a height of 5.5 tracks.
However, A7-generation options become more diverse because of differing application requirements, including AI workloads. GAA nanosheets may continue scaling, the CMOS 2.0 architecture may be used to divide the system on chip into heterogeneous functional layers, or the industry may transition to CFET. Stacking pMOS and nMOS transistors on top of one another enables standard cells to be reduced to 3 tracks, while potentially extending the conventional CMOS roadmap to the A3 node, according to the article.
imec and its partners are working on two CFET manufacturing paths: monolithic mCFET, in which the vertical structure is processed in a single sequence, and sequential sCFET, in which the upper and lower devices are formed independently using dedicated masks. sCFET simplifies some steps, but requires critical steps to be repeated and the wafer to be flipped twice, making it more difficult to align the connections between the two sides. imec therefore views mCFET as potentially the faster path to industrial adoption, while alignment accuracy remains a critical factor for sCFET.
Backside Contact Improves Bottom-pFET Performance
Connecting the source and drain regions of the bottom devices from the back of the wafer offers advantages over frontside connection, including lower contact resistance, a wider process window for the top device, reduced cell height, and less congestion in the frontside interconnect layers. However, this approach requires wafer bonding, backside substrate thinning, and a backside dielectric isolation (BDI) module.
In the conventional approach, BDI is formed from the backside near the end of the manufacturing flow. This can lead to substantial variation in the size of the bottom SiGe:B source/drain structure because its growth is affected by the bottom Si channel and the substrate beneath it. This structure also occupies space that reduces the area available for the contact metal and increases access resistance, with additional factors potentially lowering backside-contact yield.
At the 2026 VLSI Symposium, imec presented an approach that adds a frontside BDI structure beneath the source/drain while retaining a subsequent backside BDI structure. The frontside dielectric is formed early by adding a germanium-rich SiGe layer to the Si/SiGe stack, then replacing it with a dielectric during formation of the middle dielectric isolation (MDI). As a result, the bottom SiGe:B layer no longer grows in dependence on the substrate, improving uniformity in its size and contact resistance.
On an mCFET test vehicle, the new module increased the drive current of the bottom pFET devices fivefold compared with the conventional approach and reduced access resistance from 1753 to 378 Ω·µm. The survival rate of the bottom devices also increased from 45% to 85%. The article states that the process flow is believed to be applicable to sCFET as well, but the reported practical demonstration was conducted on mCFET.
Threshold-Voltage Tuning with a Lower Thermal Budget
Different circuits within a chip require different threshold-voltage (Vt) values to balance performance and power consumption. Varying the thickness and composition of the gate metals is a direct approach, but it consumes the limited space already available between nanosheets. Therefore, dipole-based tuning techniques are used by inserting a material such as lanthanum between SiO2 and HfO2 layers to change the threshold voltage through differences in the material concentration.
The dipole-last approach typically requires high-temperature processing to drive the material through the high-k dielectric layer, which does not readily align with the low-temperature replacement-metal-gate processes used in CFET. Dipole-first places the material directly on top of SiO2 and avoids high-temperature processing, but it can damage the dielectric layer during patterning.
imec proposes an intermediate approach called dipole-middle. In this approach, the dipole material is deposited on top of a first thin HfO2 layer and then stabilized through moderate thermal processing sufficient to diffuse it through the thin layer. This layer protects the SiO2 during patterning, after which the unreacted material is removed, a second HfO2 layer is deposited, and a subsequent treatment is performed. The approach keeps the overall thermal budget below that of dipole-last, particularly when multiple dipole materials are integrated.
The approach was demonstrated on a CFET-based test vehicle, but the electrical evaluation was limited to electrically accessible top nFET devices. The data showed a small and consistent Vt reduction of approximately 30 millivolts compared with a reference in which the La-oxide layer had been removed before the stabilization step.
What Do the Results Actually Demonstrate?
The results show that CFET development depends not only on the transistor structure itself, but also on a series of precise modules encompassing backside contacts, isolation, and the gate stack, in addition to DTCO studies that connect these modules to cell and circuit performance. The improvement in the bottom pFET provides direct indications of reduced resistance and improved yield, while dipole-middle offers a method for tuning Vt with better thermal compatibility.
Nevertheless, the results remain at the level of test vehicles, and the Vt-tuning demonstration did not electrically evaluate all devices in the structure. sCFET also continues to face wafer-flipping and alignment challenges, while the next part of the work will examine scalability for standard cells and SRAM. The results were produced within the European NanoIC pilot line, which targets systems-on-chip beyond 2 nanometers, making them a step in the development process rather than an announcement of commercial-production readiness.