Chips and Semiconductors

Processors, GPU units, on-device artificial intelligence, chip manufacturing, and industry news.

74 Articles

Huawei Reveals Ascend Chip Roadmap and Atlas Architecture to Expand AI Capabilities

Huawei announced new Ascend chips and Atlas SuperPoD systems designed to train and run artificial intelligence models, with launch dates spanning 2027 to 2029. The plan includes an optical interconnect architecture, while the company says its new architecture could deliver performance equivalent to 1.4-nanometer chips by 2031 without relying on comparable process-node shrinkage.

2026-09-17

Chips and Semiconductors

Vodafone Egypt Begins Commercial Use of Ericsson RAN Processor 6672 at Network Sites

Vodafone Egypt has begun commercial use of the Ericsson RAN Processor 6672, designed to run artificial intelligence workloads and support 5G networks directly at network sites. Ericsson says the processor increases processing capacity fourfold and reduces energy consumption by more than 50% compared with the previous generation.

2026-09-17

Chips and Semiconductors

The Storage Problem in the Age of AI Is Becoming a Chip Packaging Challenge

Semiconductor Engineering’s analysis finds that the expansion of AI workloads depends not only on computing capabilities, but also requires higher-density storage and packaging technologies capable of accommodating thinner NAND dies and taller structures. The article highlights hybrid bonding, die stacking, and the role of outsourced semiconductor assembly and test companies as decisive factors in turning density-increase promises into manufacturable products.

2026-09-17

Chips and Semiconductors

Why Have Materials Innovations Become a Critical Factor in Surpassing Chip Scaling Limits?

An analysis published in Semiconductor Engineering argues that the future of semiconductor manufacturing will depend not only on shrinking components, but also on developing new materials through simulation, artificial intelligence, and early collaboration among chip manufacturers, equipment suppliers, and materials suppliers. The analysis presents examples including dry manufacturing processes, photonic interconnects, and gallium nitride substrates.

2026-09-17

Chips and Semiconductors

Negative Thermal Expansion Materials Offer a Path to Reducing Chip Package Warpage

The semiconductor packaging industry is exploring negative thermal expansion materials that can reduce mismatches between the expansion of the die, substrate, and surrounding mold compound, a problem that is worsening as package and panel sizes increase. However, widespread adoption of these materials still depends on their ability to operate across a broad temperature range, mix homogeneously, and control impurities.

2026-09-17

Chips and Semiconductors

Why Is It Difficult to Build a Reliable Digital Twin for Advanced Chip Packaging?

It is not enough for a digital twin to emulate the theoretical design of a package; it must remain synchronized with what production lines actually manufacture, while linking chip, material, supplier, and test data. The article reveals that insufficient context, overlapping physical effects, and the need for continuous calibration are the main obstacles to building a digital twin for advanced chip packages.

2026-09-17

Chips and Semiconductors

Can the U.S. Midwest Build an Integrated Semiconductor Ecosystem?

Investments by Intel and SK hynix, along with quantum projects in Chicago, are driving the transformation of the U.S. Midwest into a new semiconductor hub. However, the skills shortage and the sustainability of funding will determine whether this transformation becomes a genuine industrial ecosystem or a temporary investment wave.

2026-09-17

Chips and Semiconductors

Why Is the Bus No Longer Enough to Connect Systems on Chip?

A technical paper from SignatureIP explains that growing unit counts and workload diversity, particularly in artificial intelligence, automotive, and chiplet-based designs, are driving SoC designs beyond traditional buses and crossbars toward NoC networks and directory-based coherency.

2026-09-16

Chips and Semiconductors

How PCIe Switches and Retimers Help Scale AI Infrastructure

The article examines how combining PCIe switches and retimers can build infrastructures that combine local scaling, scale-out across servers, and selective resource sharing. It also establishes practical criteria for evaluating bandwidth, latency, signal loss, power, and interoperability.

2026-09-15

Chips and Semiconductors

Thermal Analysis Moves from the Transistor Level to Data Center Architecture

Higher power density and the complexity of chiplet designs are making heat an architectural constraint that must be considered from the earliest stages, not merely tested later at the chip level. Experts from Synopsys, Silvaco, Vinci, Keysight EDA, and Siemens EDA believe that multiphysics modeling and digital twins have become essential for connecting the chip to the package, board, and system.

2026-09-15

Chips and Semiconductors

Why Is Hardware–Software Co-Design Still Distant Despite the Rise of AI?

Expert opinions from EDA and semiconductor companies explain that integrating hardware and software development faces organizational and technical obstacles, from differences between teams and tools to the difficulty of simulating complete workloads. AI may help write RTL and software, but it still lacks sufficient context to make complex architectural decisions.

2026-09-15

Chips and Semiconductors

A Model Predicts Underfill Cure and Thermal Resistance in Advanced Packaging

A study involving researchers from NIST, UCSD, and others presented a model for measuring the cure evolution of a highly filled epoxy and estimating its ability to withstand heat in advanced chip-packaging applications. The results link thermal analysis and kinetic modeling to improve reliability assessment during manufacturing and service.

2026-09-11

Chips and Semiconductors

REACH Proposes a Lower-Cost Architecture to Protect HBM from Memory Errors During AI Model Inference

Researchers from Rensselaer Polytechnic Institute and IBM introduced the REACH architecture for managing long-span error-correcting codes inside an HBM controller, targeting reduced decoding overhead in large language model inference workloads. The approach relies on inner codes for common errors and an outer code to repair parts known to be erased.

2026-09-11

Chips and Semiconductors

Why Ring Oscillators Are Not Enough to Understand Advanced Chip Behavior

The article explains how custom process monitors, supported by design-aware analytics, can move from detecting measurement deviations to inferring the factors behind changes in silicon behavior. The text presents the Global Variation Process Detector as a scalable alternative to relying on a single frequency reading.

2026-09-10

Chips and Semiconductors

Why Film Thickness Alone Is Not Enough to Control SiCr Resistors in BCD Chips

A technical article from Onto Innovation explains that measuring SiCr film thickness does not reveal all the structural and property variations that affect the performance of BCD chip resistors. It presents the use of picosecond ultrasonics together with simultaneous reflectance measurement to monitor deposition variations, particularly those associated with N₂ gas flow.

2026-09-10

Chips and Semiconductors

1-Kilowatt AI Accelerators Redefine the Meaning of Reliability Verification

Operation at the 1-kilowatt level does not represent a single test condition, as risks vary according to the workload, heat location, operating duration, and power-delivery path. Semiconductor Engineering’s analysis argues that verification must cover the chip, package, test system, and field data—not merely the detection of electrical failures.

2026-09-10

Chips and Semiconductors

Below 2 Nanometers, the Boundaries Between Chip Manufacturing Stages Fade

The transition to sub-2-nanometer manufacturing nodes is merging the roles of testing, measurement, inspection, and manufacturing, as chips become more sensitive to variations and defects. Analysis by Semiconductor Engineering indicates that managing data throughout the chip life cycle, from design to operation, has become essential for maintaining yield and reliability.

2026-09-10

Chips and Semiconductors

Silent Data Errors Redefine Processor Testing and Server Fleet Maintenance

Processors may pass conventional manufacturing tests and then produce incorrect computational results that leave no obvious trace in logs. This problem is driving the data center industry to expand testing to the system and fleet levels, with continuous hardware monitoring after deployment.

2026-09-10